We are searching for an ASIC/FPGA Synthesis Timing Specialist
for one of our clients in Ottawa
. The successful candidate will be an expert with DSP ASIC's
- Working as part of the ASIC Implementation team
- Developing and maintaining static timing restraints
- Implementation of ECO's as required
- University Degree in engineering or equivalent.
- 7 or more years of ASIC experience
- Experience with Verilog, System Verilog, OVM/UVM, VHDL and scripting languages.
- Experience with SONET, OTN, Ethernet, PCle
- Excellent communication skills
- Experience with constrained verification techniques, assertions, and functional coverage.